This invention relates generally to transition detector circuits, and more particularly, it relates to a CMOS address transition detector for generating an output pulse signal having a pulse width which is substantially constant over a wide temperature range.
Transition detector circuits are generally well known in the art for detecting logic transitions in an input signal and frequently used in computer data processing systems. However, the prior art detector circuits suffer from one or more shortcomings which have not been solved heretofore. One of the major problems experienced in the prior art detector circuits is that the output pulse produced has a pulse width which varies greatly over the temperature range for military specification of -55.degree. C. to +135.degree. C. Another problem is that many such detector circuits have a slow response time, i.e., a relatively long propagation delay between the occurrence of an address transition and the generation of the output pulse. Another difficulty associated with these prior art circuits is that they tend to consume considerable amounts of power since they have been generally formed by using bipolar or NMOS technologies.
It would therefore be desirable to provide an address transition detector for generating an output pulse signal having a pulse width which remains substantially constant with temperature variations. Further, it would be desirable to have an address transition detector which has a fast response time and has low power dissipation. The address transition detector of the present invention is constructed in fully complementary-metal-oxide-semiconductor (CMOS) devices and are connected so that no direct current path exists between the power supply and ground resulting in practically no power being consumed between input address transitions. Further, the instant address transition detector utilizes temperature compensated active resistors for controlling the output pulse width to be substantially constant over temperature variations.